1. Field of the Invention
The present invention relates to liquid crystal display devices and more particularly to a drive scheme of a liquid crystal display device with reduced drive power.
2. Description of the Related Art
In liquid crystal display devices using a liquid crystal panel of the STN scheme, a pixel drive signal thereof—that is, a drive signal for selection of each cell of the liquid crystal panel—consists essentially of a common signal that is a selected signal (scan signal) and a segment signal indicative of display data, wherein these are supplied in the form of alternate current (AC) signals.
FIG. 7 is a block diagram for explanation of an overall arrangement of drive circuitry of a liquid crystal display device. In this drawing, “LCD” is a liquid crystal panel, which is constituted from a plurality of common electrodes COM (COM1, COM2, . . . , COMn, COMn+1, . . . ) and a plurality of segment electrodes SEG (SEG1, SEG2, . . . , SEGm, SEGm+1, . . . ). A common driver D-C for driving the common electrodes COM is configured from a scan data generation circuit (scan signal generator circuit) DSS, a level shifter LS, a common-side liquid crystal drive circuit CD, and a DC/DC converter DD. The common-side liquid crystal drive circuit CD has a common voltage output circuit COP.
A segment driver D-S for driving the segment electrodes SEG is made up of an interface circuit (microcomputer interface) I/F of control signals and data (display data) input from an external signal source (a host computer or the like) and also of the power supply, a graphic RAM (GR), a gradation generator circuit GSL, and a segment-side liquid crystal drive circuit SDS. The segment-side liquid crystal drive circuit SDS has a segment voltage output circuit SOP. The DC/DC converter DD of common driver D-C generates from an externally input power supply voltage a power supply voltage(s) necessary for the common driver D-C and the segment driver D-S. A timing signal generated at the microcomputer interface I/F is utilized by the segment driver D-S and common driver D-C. At the microcomputer interface I/F, drive control signals such as a frame signal FLM and an AC-modified signal M plus a latch pulse(s) CL1 and the like are generated based on a control signal input from the external signal source (host computer or else).
FIG. 8 is a waveform diagram for explanation of drive waveforms of the related art in case a segment level changes within a scan period in the scheme for applying a pulse-width-modulated data signal voltage to a segment electrode (referred to as the PWM scheme hereinafter). In the drawing, FLM designates a frame signal, M denotes an AC-modified signal, CL1 is a latch pulse, COM (COM1, COM2, . . . , COMn) is a common electrode drive signal, SEGj representatively indicates a segment electrode drive signal. Additionally, “(COMn)−(SEGj)” denotes an applied voltage of a cell (n, j).
A common electrode is applied a selected voltage VCH within a scan period and a non-select voltage VM in the remaining time periods. Accordingly the common electrode is mostly set at the non-select voltage VM. A segment output voltage to be applied to a segment electrode changes in accordance with a display pattern. With a gradation display due to the PWM scheme, at least a specified number—this number corresponds to a gradation level number—of tiny subdivided or “sliced” time periods are provided within a single selected period H (of each row), wherein a segment electrode output level is changed at an appropriate timing that is in conformity with the number of gradation levels being displayed.
In FIG. 8, the gradation number is set at 16 levels of from “1” (white) up to “16” (black), with the single selected period H being divided or sliced into 16 tiny subordinate periods-say, sub-periods. And, the common electrodes are sequentially applied a selected voltage VCH in an order from the first row thereof. In addition, a segment electrode SEGj in the j-th column is applied a level VSL corresponding to the white display as the segment electrode output for displaying the seventh level within 7 subperiods and also a level VSH corresponding to the black display for 9 subperiods. Note here that upon changing of the AC-modified signal M, the resultant correspondence relationship becomes reverse in such a way that the level corresponding to the white display is set at VSH whereas the level corresponding to the black display is at VSL.
Here, a voltage being applied between the segment electrode and common electrode at the cell (n, j) is given as “(COMn)−(SEGj).” Considering the case of n=3 which is an example of FIG. 8, the common electrode drive signal COMn at the n-th row is such that the selected voltage VCH is applied at a time of the n-th selected period whereas the non-select voltage VM is applied within the other periods. Although it becomes a non-select period at the cell (n, j) at a time of the first selected period, a voltage being applied between the segment electrode and common electrode at this cell becomes (VM−VSL) within the first 7 subperiods and becomes (VM−VSH) within the remaining 9 subperiods. Here, voltage setup is done to permit establishment of (VM−VSL)=(VSH−VM). Accordingly, at this cell, the voltage being applied between the segment electrode and common electrode changes from (VSH−VM) to (VM−VSH) upon switching of the voltage of the segment drive signal SEGj within a non-select period(s).
On the other hand, at a time of the n-th selected period, this cell becomes a selected period due to application of a selected voltage VCH to its common electrode, resulting in the voltage applied between the segment electrode and common electrode at this cell becoming (VCH−2VM+VSH) within an ON period 7/16 which is the initial white display and then becoming (VCH−VSH) within an OFF period 9/16 that is its subsequent black display.
FIG. 9 is a waveform diagram for explanation of another pattern of the related art drive waveforms. Here, an example is shown in case the AC-modified signal M was changed from the n-th selected period while displaying the white of gradation 1. Because the white of gradation 1 is being displayed, a segment drive signal SEGj is not yet changed along the way of a single selected period; however, as the AC-modified signal M is changing, the segment drive signal potentially changes from VSH to VSL from the n-th selected period. An application voltage at the cell (n, j) becomes (VCH−2VM+VSH) within the n-th selected period. At this time the applied voltage changes from (VSH−VM) to (VM−VSH) at a cell with the non-select voltage applied thereto such as a cell (1, j) by way of example, although not specifically depicted herein.
Here, electrical power consumption of the liquid crystal display device with the drive waveforms generates upon charge-up to the liquid crystal panel LCD. When the drive voltage of the segment electrode (segment drive voltage) changes, it changes into a state which permits accumulation or storage of electrical charge carriers of the same significance with opposite signs between it and an opposing common electrode applied by the non-select voltage. More specifically, certain ones wherein one of them is the charge of “+” whereas the other is the charge of “−” prior to a change of the segment drive voltage become the state in which one becomes the state of “−” and the other is of “+”. At this time, half of a consumed current is used to set the charge between opposite electrodes in a zero state. In view of the fact that common electrodes applied by nor selected voltage are greater in number than common electrodes with the selected voltage applied thereto and that in the PWM scheme the segment drive voltage varies frequently, the power consumption in such a state change becomes noticeable. A current therefor is supplied from the power supply, which results in a bar to reduction of power consumption—this has been one of problems to be solved.
On the other hand, although several power consumption reduction techniques of the related art are taught from and suggested by JP-A-11-326863, JP-A-11-194314, JP-A-9-243998, JP-A-9-2121317 and JP-A-8-263013, these related art techniques are hardly directed to PWM-scheme liquid crystal display devices.